Retrospective Higher-Order Markov Processes for User Trails

Users form information trails as they browse the web, checkin with a geolocation, rate items, or consume media. A common problem is to predict what a user might do next for the purposes of guidance, recommendation, or prefetching. First-order and higher-order Markov chains have been widely used methods to study such sequences of data. First-order Markov chains are easy to estimate, but lack accuracy when history matters. Higher-order Markov chains, in contrast, have too many parameters and suffer from overfitting the training data. Fitting these parameters with regularization and smoothing only offers mild improvements. In this paper we propose the retrospective higher-order Markov process (RHOMP) as a low-parameter model for such sequences. This model is a special case of a higher-order Markov chain where the transitions depend retrospectively on a single history state instead of an arbitrary combination of history states. There are two immediate computational advantages: the number of parameters is linear in the order of the Markov chain and the model can be fit to large state spaces. Furthermore, by providing a specific structure to the higher-order chain, RHOMPs improve the model accuracy by efficiently utilizing history states without risks of overfitting the data. We demonstrate how to estimate a RHOMP from data and we demonstrate the effectiveness of our method on various real application datasets spanning geolocation data, review sequences, and business locations. The RHOMP model uniformly outperforms higher-order Markov chains, Kneser-Ney regularization, and tensor factorizations in terms of prediction accuracy

A Clock and Data Recovery Circuit for Optical Communications in 0.18 m CMOS

The amount of data transmitted over the global communications networks has experienced a dramatic increase over the last years, mainly driven by the exponential growth of the Internet. For this reason, increasingly faster and more reliable circuits are needed to allow a correct performance at speeds in the range of the Gbps. The superior power characteristics and overall performance make optical fiber the preferred choice to implement the channel in communications links, giving rise to the concept of optical communications. Due to their bandwidth limitations, in a typical optical communcations link data cannot be transmitted with a timing reference; the clock signal that allows its correct interpretation has to be extracted at the receiver in a block called clock and data recovery circuit (CDR). Typically, a CDR circuit is a closed-loop system that generates an oscillating signal capable of tracking the phase of the incoming data stream; as well, it uses the generated clock signal to regenerate the data stream, minimising the effects of non-idealities during transmission. This paper presents the design of a CDR circuit intended to meet the 10GBase-LX4 Ethernet specifications for continuous operation at 3.125 GHz, designed in a standard 0.18 m CMOS technology provided by UMC. A detailed description of the full CDR circuit and the different blocks taking part in it will be provided, emphasising the requirements that each of them must satisfy. Finally, the correct performance of the proposed CDR circuit will be analysed by means of an extensive set of post-layout simulations

A 4-μW 0.8-V Rail-to-Rail Input/Output CMOS Fully Differential OpAmp

This paper presents an ultra low power rail-to-rail input/output operational amplifier (OpAmp) designed in a low cost 0.18 μm CMOS technology. In this OpAmp, rail-to-rail input operation is enabled by using complementary input pairs with gm control. To maximize the output swing a rail-to-rail output stage is employed. For low-voltage low-power operation, the operating transistors in the input and output stage are biased in the sub-threshold region. The simulated DC open loop gain is 51 dB, and the slew-rate is 0.04 V/μs with a 10 pF capacitive load connected to each of the amplifier outputs. For the same load, the simulated unity gain frequency is 131 kHz with a 64º phase margin. A common-mode feed-forward circuit (CMFF) increases CMRR, reducing drastically the variations in the output common mode voltage and keeping the DC gain almost constant. In fact, their relative error remains below 1.2 % for a (-20ºC, +120ºC) temperature span. In addition, the proposed OpAmp is very simple and consumes only 4 μW at 0.8 V supply

Conversion of an industrial cutaway peatland to a Betulacea family tree species plantation

ArticleTo evaluate the potential of establishing a deciduous tree plantation on an industrial cutaway peatland over an 8 ha large experimental site was established in the central part of Latvia and silver birch (Betula pendula Roth) and black alder (Alnus glutionsa (L.) Gaertn.) tree species were planted. As it is a harsh and unfavorable environment wood ash, otherwise a waste product, was used as a fertiliser and liming material in three applications (5, 10 and 15 t ha-1 ). In comparison with control, fertilised soils had higher Ca, Mg, P amounts, whilst the most substantial difference was seen in the amount of K. Application of wood ash also considerably increased soil pH from 3.5 (Control) to 5.9 (15 t ha-1 ). Even though showing reduced growth in unfertilised soil both alder and birch seedling survival rate was higher than 80%. The highest survival rate for birch was under wood ash treatment, while alder under 10 t ha-1 wood ash fertiliser treatment showed the lowest survival rate i.e. 81%. In total, more than 60 naturally occurring vegetation species were observed in the first and the second year of sites establishment after fertilisation. Species as Betula pendula, Betula pubescens, Populus tremula, Pinus sylvestris, Salix spp. often occurred from natural vegetation regeneration. Already after one year of vegetation succession increase in tree and shrub species cover was observed, suggesting perhaps such areas can be naturally afforested thus creating a more heterogeneous forest stand. In such a way sustaining economic use of land resources after peat extraction while providing other ecosystem services

CMOS Receiver Front-End Architecture for High-Speed SI-POF Links

This works presents a new CMOS analog front-end for short-reach high-speed optical communications which compensates the limited bandwidth of POF channels and is suitable for the required large area photodetectorf The proposed pseudo-differential architecture, formed by a preamplifier and an equalizer, has been designed in a standard 0.18-μm CMOS process with a 1-V supply voltage targeting gigabit transmission for NRZ modulation. The preamplifier is based on the flipped voltage follower stage to attain a very low input resistance in order to handle the large phodiode capacitance (3 pF). The equalizer can adjust the high-frequency boosting and the gain, to compensate for the variation of the characteristics of the channel due to length of the fiber, connections, etc. causing subtantial changes of the fiber bandwidth. Reliable electrical models are employed for a Mitsubishi GH SI-POF with 10-m to 50-m length and for a S5972 silicon photodiode from Hamamatsu suitable for such a fiber due to its large diameter (0.8 mm) and responsivity at 650 nm (0.44A/W). The bandwidth of the received signal can be enhanced from 100 MHz to 1.4 GHz and from 300 MHz to 1.4 GHz for a 50-m and 10-m POF respectively. The proposed circuit shows a transimpedance of 41.5 dBΩ while the theoretical sensitivity from noise performance is below -7.5 dBm with a BER = 10-12. The power consumption is below 16 mW from 1-V supply voltage. In conclusion it targets 1.25 Gbps through a 1-mm SI-POF up to 50-m length with a commercial Si PIN photodiode

Low-power 3V single supply lock-in amplifier

In extreme high noise level environments, linear filtering is not a suitable processing method and special techniques for accurately extracting sensor signal information should be considered. An interesting possibility are lock-in amplifiers (LIA), which use the phase sensitive detection technique (PSD) to take out the data signal at a specific reference frequency fo while noise signals at frequencies other than fo are rejected and do not affect significantly the measurement. Current commercial LIAs are expensive, heavy and power consuming devices, which preclude their use in portable sensing systems. Thus, this work analyses the possibility of exporting this technique to low-power low-voltage (LPLV) embedded applications. In particular, the aim is to implement a signal conditioning lock-in architecture suitable for 3V single battery-operated wireless sensor nodes. This implies to re-design all the processing elements in single supply -most reported LIAs are designed using dual power supply- and compatible with the power requirements of a wireless sensor network node. Further, looking for a compact LPLV solution, instead of a traditional sinusoidal input, a square wave input is considered, which can be directly obtained from the embedded microcontroller, thus avoiding blocks like a sinusoidal oscillator or function generator. Figure 1 shows the proposed block diagram and a photograph of the implemented device. Experimental results for signals buried in white noise, flicker noise, interference contamination and common-mode voltage contamination confirm the capability of the proposed solution to recover information from signal to noise ratios down to 24 dB with errors below 6% with an average power consumption of only 5 mW in full operation, being able to process signals with frequencies up to 43 kHz, as shown in Figure 2

Voltage-to-Frequency Converter for Low-Power Sensor Interfaces

This work presents a low-power rail-to-rail temperature compensated voltage-to-frequency converter (VFC) which constitutes the last stage of a sensor read-out interface targeting wireless sensor networks (WSN) applications. These quasi-digital converters are now receiving great interest, since they combine the simplicity of analog devices with the accuracy and noise immunity proper to digital signal processing; besides, frequency output is directly driven to the embedded node microcontroller C, which next performs the A/D conversion using its internal timers. A first read-out interface prototype using low-voltage low-power commercial components shows that the VFC means 99 % of the total interface consumption in read-out mode. Further, existing CMOS VFCs in the form of ASICs have a rather limited input range and an unsuitable output frequency span for typical C clock frequencies used in WSN. Hence, a novel full custom VFC solution is needed, fullfilling the main requirements of rail-to-rail operation, to take advantage of the full supply voltage range to optimize the output frequency resolution, and low-power low-voltage operation to have a power supply compatible with conventional WSN batteries while maximizing the operating life of the sensor node. Experimental results for a 0.18–μm 1.2–V CMOS VFC implementation show for an input range of (0–1.2 V) an output frequency range of (0.1–1.0 MHz), adequate to digitize the signal with the direct counting method in the sensor node μC achieving 13 bits resolution. It has a power consumption of 60 μW (35 nW in sleep mode) and it is temperature insensitive for a temperature range of (-40, 120 ºC)

Sensor-Based Seeds for a Chaotic Stream Cipher

In this paper we have used a surface micromachined capacitive accelerometer in order to generate seeds that are suitable for secure communications between wireless smart sensors for IoT networks. These seeds have then been used in a chaotic stream cipher based on a Modified Logistic Map and a Linear Feedback Shift Register. The sequences generated by the chaotic stream cipher have been subjected to the randomness NIST tests. All the tests have been passed, proving that the proposed approach could be used for secure communications

HypTrails: A Bayesian Approach for Comparing Hypotheses About Human Trails on the Web

When users interact with the Web today, they leave sequential digital trails on a massive scale. Examples of such human trails include Web navigation, sequences of online restaurant reviews, or online music play lists. Understanding the factors that drive the production of these trails can be useful for e.g., improving underlying network structures, predicting user clicks or enhancing recommendations. In this work, we present a general approach called HypTrails for comparing a set of hypotheses about human trails on the Web, where hypotheses represent beliefs about transitions between states. Our approach utilizes Markov chain models with Bayesian inference. The main idea is to incorporate hypotheses as informative Dirichlet priors and to leverage the sensitivity of Bayes factors on the prior for comparing hypotheses with each other. For eliciting Dirichlet priors from hypotheses, we present an adaption of the so-called (trial) roulette method. We demonstrate the general mechanics and applicability of HypTrails by performing experiments with (i) synthetic trails for which we control the mechanisms that have produced them and (ii) empirical trails stemming from different domains including website navigation, business reviews and online music played. Our work expands the repertoire of methods available for studying human trails on the Web.Comment: Published in the proceedings of WWW'1